Index of /~dst/DeCSS/Gallery/DAH

      Name                    Last modified       Size  Description


[DIR] Parent Directory        04-Jan-2003 01:19      -  
[DIR] C/                      08-Mar-2001 00:24      -  
[DIR] Sketches/               09-Mar-2001 04:17      -  
[DIR] Verilog/                08-Mar-2001 04:40      -  

DeCSS in Verilog: decss.v

This directory contains a design for DeCSS in Verilog, a Hardware
Description Language.[1] This design can be simulated by a Verilog
interpreter (I include a copy of a redistributable demo version for
DOS) and it could also be synthesized to physical hardware[2].  At the
same time, it is human-written, human-readable.  This helps illustrate
the continuum between human language, computer language, and hardware.

Verilog is a very different language from C, Perl, etc; in Verilog
(and physics), everything happens at once, unless you make it
sequential.

This design is based on the C implementation CSSdescramble() found in
c-anonymous.c.  My DeCSS_Test.c contains a main() which calls the
CSSdescramble(unsigned char *sec,unsigned char *key) function.  This C
was used to generate known-good output for verification of the design,
as well as tracing the algorithm's internal state during development &
debug.  DeCSS/C/Debug/DeCSS.exe generates one such file.

This Verilog implementation of DeCSS consists of the human-readable,
synthesizable-to-hardware source file "decss.v" and a testbench which
exercises that module, "test_decss.v".  The 5 CSTables used in
c-anonymous.c were ported to ROMs in this design; some of these could
be eliminated or shrunk if their internal structure were exploited,
but I didn't do that. The 5 CSTable ROMs are implemented as
CSTable_N.v each of which reads in a file CSTable_N.txt to initialize
its contents, N=1..5

Circuit I/O & Timing

This decss circuit has the following inputs (in addition to clock and
reset): An 8 bit 'key' input, an 8 bit 'data' input, and a 'start' line.
The circuit has the following outputs: an 8 bit data output bus, and a
single 'Data Valid' line which signals that the data on the output bus
is valid and that the data input should change.

To use the circuit, put Key[0] on the key bus, Sec[0x54] on the data
bus, and assert Start for one clock.  On successive clocks, present
Key[1] and Sec[0x55], Key[2] and Sec[0x56], etc.

Then present Sec[0x80] on the data input bus and wait for Data Valid
to be asserted.  When it is, Data Output is valid, and Data Input
should have the next value placed on it.  One byte requires 5 clocks.
The circuit stops after 0x800-0x80 bytes, like the function I derived
it from, which the 'user' is responsible for counting.  However, as a
stream cipher, this is arbitrary.

-DAH (MIT '86)
07 March 2001 


C/
Sketches/
Verilog/

Synthesizable Logic:
decss.v

Testbench: 
test_decss.v

Tables: 

CSTable_1.txt
CSTable_1.v
CSTable_2.txt
CSTable_2.v
CSTable_3.txt
CSTable_3.v
CSTable_4.txt
CSTable_4.v
CSTable_5.txt
CSTable_5.v



Script to run Verilog interpreter on project: 
v.bat

Verilog interpreter: 
veriDOS.exe







[1] http://www.ovi.org/ 

[2] You need a synthesis tool like Synopsis or
Synplicity and target either an FPGA or an ASIC process.  You'd also
have to assign physical pins to logical ports.  This design uses about
3000 gates, not including ROMs, and 50 Mhz operation (10 Mbytes/sec)
is possible in an FPGA.  It would be under a square millimeter; but
you can fit a CPU into that, and in some systems a general purpose CPU
might be more appropriate.